ISSCC: SanDisk builds NAND flash chips with 3-bit cells
Flash memory cards are set to get an increase in capacity. In order to save silicon area and thus reduce production costs, the multi-level cell (MLC) technique is used for flash memory chips. Until now, known MLC components have mainly stored two bits in each cell.
For its NAND flash-compatible ORNAND flashes, however, Spansion is already using MirrorBit Quad. These 90nm chips currently store a maximum of 2GB, while Spansion makes a 4 gigabit component as a dual-die package. For some weeks now, the new 65nm fabrication plant has been supplying samples of 1 gigabit ORNAND chips.
Several firms are working on NAND flash structures with 4-level cells, but SanDisk is now initially using the intermediate step x3 MLC with three bits per cell, developed jointly with its partner Toshiba, for a 16 gigabit chip. Series production using a 56nm process is to begin in April at the latest. With x3 MLC, SanDisk plans to make 20 per cent more dies per wafer than would be possible with x2 MLC technology, but SanDisk won't reveal the precise die size.
In comparison with single-level cell (SLC) NAND flashes, which are more expensive because of their larger die areas, but MLC memory chips do have disadvantages. The number of write cycles that each individual cell survives is typically around 10,000 for MLCs, but the figure for SLCs is usually 100,000. Error correction for MLCs requires a more expensive 4-bit ECC technique, whereas 2-bit ECC is sufficient for SLCs. The higher cost of signal processing reduces the data transfer rate. At the ISSCC, SanDisk reports a coming x4 MLC NAND flash, also with 16 gigabit capacity, which is to be writeable at up to 34MB/s, thanks to a special bitline architecture. A closely related chip with x2 MLC and half the capacity, on the other hand, is to achieve more than 60MB/s. SanDisk quotes only 8MB/s for writing to the x3 MLC NAND flash. SLC NAND flashes are still commonly built into fast solid-state discs (SSDs). Intel and Micron have also announced ONFI 2.0 NAND flashes with a capacity of eight gigabits and a write-data transfer rate of up to 100MB/s at ISSCC 2008.
For other applications, speed is less important than the physical size of the chip, so SanDisk and Toshiba plan to build x4 MLC NAND flashes using a 43nm process, to accommodate 16 gigabits of data in 120mm² of silicon. A chip like this, with a capacity of 2 gigabytes, would then also fit into microSD memory cards. Up to 16 chips can be stacked to a height of 1.4 millimetres] in multi-die packages.
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