ISSCC: Intel publishes details about Silverthorne

Intel announced further details of its especially energy-efficient Silverthorne processor at the International Solid-State Circuits Conference (ISSCC). Silverthorne only consumes 0.6 to 2W depending on the load. The 45nm CPU with a die surface of 25mm[sup]2[/sup] uses only 47 million transistors, far fewer than the 412 million transistors of the current Core 2 Duo with a Penryn core (also with a 45nm structure width). Despite this, Silverthorne is fully x86-compatible and supports the x64 (AMD64) and SSE3 (Digital Media Boost) instruction sets. Intel's VT also supports virtualisation solutions.

Silverthorne marks a step away from Intel's out-of-order pipeline architecture; the new processors strictly handle commands in order. The processors do, however, offer HyperThreading in order to process two independent commands simultaneously, thus improving utilisation for each "virtual" core and counteracting memory delays. Intel claims that Silverthorne runs at clock speeds up to 2GHz, though this doesn't indicate its performance in comparison with other processors because of the new processor's in-order architecture. Intel promises that performance will be roughly at the level of the first Pentium M with a Banias core.

Even when running at 100 per cent utilisation, Silverthorne will reportedly only consume 2 W — and a 60th of that in the deep power-down mode.

Silverthorne uses the power-saving C6 mode used in Core 2 Duo, in which the CPU can switch off almost all functional units. The L1 caches (32kB of instructions, 24kB of data) and L2 cache (the 512kB) are emptied beforehand. The chip also has 10.5kB of special C6 memory, which only needs a 0.3V supply to store the status of caches and register files. Intel says that the switch to and from C4, the next power level up, takes less than 100µs. For its caches, Intel uses eight-transistor cells, which consume less power than cells with six transistors.

In addition to the classic GTL mode, the front side bus (FSB533) also supports a special CMOS mode that reportedly consumes two and a half times less energy than GTL. If the CPU is in the C6 mode, Silverthorne makes do with only 21 of the 203 data pins under current. Overall, the Silverthorne case has 441 µFCBGA contacts. Intel did not say whether the Poulsbo chipset, which like Silverthorne is part of the Menlow platform, supports the CMOS-FSB, nor was any information provided on the platform's official name or the planned market launch. At last year's IDF, Intel announced that the launch would take place in the first quarter of 2008.

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