Hot Chips: the third Dragon CPU
The Institute of Computing Technology (ICT) of the Chinese Academy of Sciences announced at the 20th Hot Chips Conference that it is planning to move the third generation of the Godson CPU closer to the x86 instruction set. While internally the chip will keep on working with a MIPS64 instruction set it will translate the x86 binaries itself and then execute them – ten times faster than emulation in software.
Previous Godson CPUs
Also new for the Godson is a heterogeneous multicore design: the chip consists of individual nodes, each node having four cores, four L2 cache blocks – size still unclear – and an 8x8 crossbar switch. Four connections each go to the cores and to the cache. The remaining eight are available for connecting to other nodes. The researchers intend to arrange the nodes in a mesh so that there are two links for each of the four points of the compass. Outside of the node mesh, DMA controllers take care of PCIe and HyperTransport connections. Probably only non-coherent HT 1.0 will be retained initially. The DMA controllers still have a few tricks up their sleeves, such as prefetch and matrix transposition. The memory controllers are attached to the caches of the individual nodes via further switches. A directory-based coherence protocol safeguards the data in the caches. These can however be reconfigured for use as internal RAM, enabling Godson to also work as a stream processor.
Another noteworthy feature is that there are two different types of core. The general purpose core (GS464) largely corresponds to the one used in current Godson 2 chips. It has an L1 cache of 2 × 64 kilobytes and sits on a four-stage super-scalar out-of-order pipeline. But more than 200 new instructions are added on to the MIPS64 instruction set so that x86 code can be executed efficiently. The additional instructions enlarge the die by approximately four per cent.
A Godson 3 chip is to consist of many nodes in future, each with four cores.
For certain tasks, such as LINPACK, signal processing, and scientific calculations, there are also multiple purpose cores (GStera). They consist of 8 to 16 multiply-accumulate (MAC) units, a gigantic register file, and an AXI interface. AXI is described in ARM's AMBA 3 Specification. A node made of multiple purpose cores should run at up to 16 GFLOPS – four times as fast as one made of general purpose cores.
A first test chip with the multi purpose cores is not due until 2009.
Godson 3 will be manufactured in a 65-nm process by ST Micro. Before the end of this year the researchers hope to produce their first test chip, consisting of just one node with four GS464 cores. It is planned to have a clock frequency of 1 GHz and total dissipated power (TDP) of 10 watts. A chip with two nodes, whose second node contains four multiple purpose cores, is to follow in 2009. TDP will then rise to 20 watts. It is still unclear when a two-dimensional mesh will actually be cast in silicon.
Godson 2G is to have its own graphics core.
The ICT spokesperson made it clear that developing its own processor is in China's strategic interests, and that the plan is to catch up step by step with the lead of Intel and others. So far, each generation of Godson has tripled performance, thus reducing Intel's lead. The Godson 2F, which has an integrated memory controller, is currently on the market. The roll out for Godson 2G is due to begin this month. Godson 2H, which has an integrated graphics core and manages without Southbridge, is set for the first half of 2009. Around 200 developers are working on the Godson hardware, and still others on compilers, software and so forth.
(trk)
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